Datasheet

Auxiliary analog and digital functions ST7538Q
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6.12 Power-up procedure
To ensure ST7538Q proper power-Up sequence, PAVcc, AVdd and DVdd Supply has to fulfil
the following rules:
PAVcc rising slope must not exceed 100V/ms.
When DVdd is below 5V/3.3V and AVdd is below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd <
1.2V.
When AVdd and DVdd supplies are connected to VDC the above mentioned relation is
guarantied if VDC load < 100mA and if the filtering capacitor on VDC < 100uF.
If DVdd is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if DVdd load <
50mA and the filtering capacitor on DVdd < 100uF the second relation can be ignored .
Figure 24. Power-UP sequence