Datasheet

ST7538Q Functional description
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Figure 5. Data reception -> data transmission -> data reception
5.6 Control register access
The communication with ST7538Q Control Register is always synchronous. The access is
achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus
REG_DATA Line.
With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control
Register MSB first. The ST7538Q samples the TxD line on CLR/T rising edges. The control
Register content is updated at the end of the register access section (REG_DATA falling
edge).
In Normal Control Register mode (Control Register bit 21=”0”, see Tabl e 1 1 ) if more than 24
bits are transferred to ST7538Q only latest 24 bits are stored inside the Control Register. If
less than 24 bits are transferred to ST7538Q the Control Register writing is aborted (in this
case if at least 16 bits are provided REGOK line will be activated).
In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations
(for example because of surge or burst on mains), in Extended Control Register mode
(Control Register bit 21=”1” see Ta bl e 1 1) exactly 24 or 48 bits must be transferred to
ST7538Q in order to properly write the Control Register, otherwise writing is aborted and if
at least 16 bits are provided REGOK line will be activated. If 24 bits are transferred, only the
first 24 Control Register bits (from 23 to 0) are written.
With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.
The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register
mode 24 bits are transferred from ST7538Q to the Host. In Extended Control Register mode
24 or 48 bits are transferred from ST7538Q to the Host depending on content of Control
Register bit 18 (with bit 18 = ”0” the first 24 bits are transferred, otherwise all 48 bits are
transferred, see Ta bl e 1 1 ).
T
CC
T
DS
T
CR
T
CR
T
DH
T
S
T
H
T
B
T
CC
CLR_T
RxD
RxTx
TxD
REG_DATA
D03IN1402
BIT23 BIT22