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July 2006 Rev 1 1/44

ST7538Q

FSK power line transceiver

General features

■ Half duplex frequency shift keying (FSK)

transceiver

■ Integrated power line driver with programmable

voltage and current control

■ Programmable interface:

– Synchronous

– Asynchronous

■ Single supply voltage (from 7.5 up to 12.5V)

■ Very low power consumption (Iq = 5mA)

■ Integrated 5V voltage regulator (up to 50mA)

with short circuit protection

■ Integrated 3.3V voltage regulator (up to 50mA)

with short circuit protection

■ 3.3V or 5V digital supply

■ 8 programmable transmission frequencies

■ Programmable baud rate up to 4800BPS

■ Receiving sensitivity up to 250µVrms

■ Suitable to application in accordance with EN

50065 CENELEC specifications

■ Carrier or preamble detection

■ Band in use detection

■ Programmable 24 or 48 bit register with

security checksum

■ Mains zero crossing detection and

synchronization

■ Watchdog timer

■ Output voltage freeze

■ 8 or 16 bit header recognition

■ UART/SPI host interface

■ ST7537 compatible

Description

The ST7538Q is a Half Duplex

synchronous/asynchronous FSK Modem

designed for power line communication network

applications. It operates from a single supply

voltage and integrates a line driver and two linear

regulators for 5V and 3.3V. The device operation

is controlled by means of an internal register,

programmable through the synchronous serial

interface. Additional functions as watchdog, clock

output, output voltage and current control,

preamble detection, time-out, band in use are

included. Realized in Multipower BCD5

technology that allows to integrate DMOS, Bipolar

and CMOS structures in the same chip.

TQFP44 Slug Down

www.st.com

Order codes

Part number Package Packaging

ST7538Q TQFP44 Slug Down Tube

ST7538QTR TQFP44 Slug Down Tape and reel

Summary of content (44 pages)

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ST7538Q FSK power line transceiver General features ■ Half duplex frequency shift keying (FSK) transceiver ■ Integrated power line driver with programmable voltage and current control ■ Programmable interface: – Synchronous – Asynchronous TQFP44 Slug Down ■ Single supply voltage (from 7.5 up to 12.5V) ■ Very low power consumption (Iq = 5mA) ■ Integrated 5V voltage regulator (up to 50mA) with short circuit protection ■ Integrated 3.
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Contents ST7538Q Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical data . . . .
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ST7538Q 6 Contents Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 Zero crossing detection . . . . . . . . . . . . .
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Block diagram ST7538Q 1 Block diagram Figure 1.
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ST7538Q Pin settings 2 Pin settings 2.1 Pin connection N.C. REG_DATA PG GND C_OUT N.C. C_PLUS C_MINUS REG_OK TEST1 N.C. Pin Connection (Top view) 44 43 42 41 40 39 38 37 36 35 34 TEST2 TXD 5 29 VSENSE GND 6 28 AVDD TOUT 7 27 XIN CLR/T 8 26 XOUT BU 9 25 SGND DVDD 10 24 ATO MCLK 11 23 CL 12 13 14 15 16 17 18 19 20 21 22 ATOP2 30 PAVCC 4 PAVSS RXFO RxTx ATOP1 31 N.C.
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Pin settings 2.2 ST7538Q Pin description Table 1. Pin description Pin N° Name 1 CD_PD 2 Type Description Digital/Output Carrier, Preamble or Frame Header Detect Output. "1" No Carrier, Preamble or Frame Header Detected "0" Carrier, Preamble or Frame Header Detected DVss Supply Digital Ground 3 RxD Digital/Output RX Data Output. 4 RxTx Digital/Input with internal pull-up Rx or Tx mode selection input. "1" - RX Session "0" - TX Session 5 TxD Digital/Input TX Data Input.
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ST7538Q Pin settings Table 1. Pin description (continued) Pin N° Name 25 SGND Supply Analog Signal Ground 26 XOUT Analog Output Crystal Output 27 XIN Analog Input Crystal Oscillator Input - External Clock Input 28 AVdd Supply Analog Power supply.
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Electrical data ST7538Q 3 Electrical data 3.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Unit PAVCC Power Supply Voltage -0.3 to +14 V AVdd Analog Supply Voltage -0.3 to +5.5 V DVdd Digital Supply Voltage -0.3 to +5.5 V -0.3 to +0.3 V Digital input Voltage DVss - 0.3 to DVdd +0.3 V VO Digital output Voltage DVss - 0.3 to DVdd +0.3 V IO Digital Output Current -2 to +2 mA AVss - 0.3 to AVdd+0.3 V Voltage Range at RAI, ZCIN Inputs -AVdd - 0.
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ST7538Q 3.2 Electrical characteristics Thermal data Table 3. Thermal data Symbol Parameter TQFP44 with slug Unit RthJA1 Maximum Thermal Resistance Junction-Ambient Steady state (1) 35 ° C/W RthJA2 Maximum Thermal Resistance Junction-Ambient Steady state (2) 50 ° C/W 1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB 2. It's the same condition of the point above, without any heatsinking surface on the board. 4 Electrical characteristics Table 4.
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Electrical characteristics ST7538Q Table 4.
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ST7538Q Electrical characteristics Table 4.
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Electrical characteristics ST7538Q Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤TA ≤ 85°C, TJ < 125 °C, fc = 86kHz, other control register parameters as default value, unless otherwise specified) Symbol CCL CCLTH CCLHYST TRxTx TALC TST Parameter Test condition Min Input capacitance on CL pin Current control loop reference threshold on CL pin Typ Max 80 Unit pF Figure 14 1.80 1.90 2.
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ST7538Q Electrical characteristics Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤TA ≤ 85°C, TJ < 125 °C, fc = 86kHz, other control register parameters as default value, unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit -5% 5.05 +5% V 4.3 4.5 4.
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Electrical characteristics ST7538Q Table 4.
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ST7538Q Functional description 5 Functional description 5.1 Carrier frequencies ST7538Q is a multi frequency device: eight programmable Carrier Frequencies are available (see Table 5). Only one Carrier could be used a time. The communication channel could be varied during the normal working Mode to realize a multifrequency communication. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 5. ST7538Q Channels List 5.
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Functional description 5.3 ST7538Q Mark and space frequencies Mark and space communication frequencies are defined by the following formula: F ("0") = FCarrier + [∆F]/2 F ("1") = FCarrier - [∆F]/2 ∆F is the Frequency Deviation. With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the Baudrate value (∆F = 0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (∆F = Baudrate). The minimal Frequency Deviation is 600Hz. Table 7.
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ST7538Q Functional description Table 7. ST7538Q synthesized frequencies Exact Carrier Frequency [Hz] Baud Frequency Deviation (Clock=16MHz) Rate (KHz) “1” “0” 72 600 1200 2400 4800 76 600 1200 2400 4800 5.4 -- Exact Carrier Frequency [Hz] Frequen Baud Deviation (Clock=16MHz) cy Rate (KHz) “1” “0” 110 1 71777 72266 0.5 71777 72266 1 71452 72591 0.5 71452 72591 1 70801 73242 0.5 70801 73242 1 69661 74382 -- 1200 2400 4800 132.5 1 75684 76335 0.
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Functional description ST7538Q In Data Reception Mode: 5.5 – Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7538Q recovers the bit timing according to the BaudRate Selected. – Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data reception line (RxD line).
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ST7538Q Functional description The UART interface allows to connect an UART compatible device instead SPI interface allows to connect an SPI compatible device. The allowed combinations of Host Interface/ST7538Q Mains Access are: Table 9. Host Interface / ST7538Q mains access combinations Host Device interface type UART/SPI pin UART Mains access Communication mode Asynchronous “1” Transmission X UART “1” Reception X SPI “0” Transmission X SPI “0” Reception X Synchronous X(1) 1.
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Functional description 5.5.1 ST7538Q Communication between host and ST7538Q The Host can achieve the Mains access by selecting REG_DATA = ”0” and the choice between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx =“1” ST7538Q receives data from mains, if RxTx = ”0” ST7538Q transmits data over the mains).
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ST7538Q Functional description Figure 5. Data reception -> data transmission -> data reception TCC TCC CLR_T TB TDS TDH RxD REG_DATA TCR TCR RxTx TSTH TxD BIT23 BIT22 D03IN1402 5.6 Control register access The communication with ST7538Q Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus REG_DATA Line. With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control Register MSB first.
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Functional description ST7538Q Figure 6. Data reception -> control register read -> data reception timing diagram TCC TCC CLR_T TDS TDH TDS RXD TDH BIT23 TB BIT22 TCR REG_DATA TCR RxTx D03IN1404 Figure 7. Data reception -> control register write -> data reception timing diagram TCC TCC CLR_T TDS TB TDH RxD TCR TCR REG_DATA TCR TCR RxTx TSTH TxD BIT23 BIT22 D03IN1403 Figure 8. Data transmission -> control reg.
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ST7538Q 5.7 Functional description Receiving mode The receive section is active when RxTx Pin = ”1” and REG_DATA = 0. The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio.
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Functional description ST7538Q Figure 10. ST7538Q PLL lock-in range CLR/T RxD D03IN1417 LOCK-IN RANGE 5.7.3 Carrier/preamble detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: 5.7.
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ST7538Q Functional description Figure 11. CD_PD timing during RX TDCD TCD TDCD TCD CD_PD RAI demodulation active on RxD pin noise demodulated RxD (UART/SPI="1") noise demodulated RxD (UART/SPI="0") D03IN1418 Figure 12. Receiving path block diagram RXFO 31 Bits 3-4 Bits 3-4 & 22 3 Bits 3-4 &14 8 PLL Bits 18-21 & 24-47 1 CD_PD Low Pass DIGITAL FILTER Bits 9-10 HEADER RECOGN.
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Functional description 5.8 ST7538Q Transmission mode The transmit mode is set when RxTx Pin = ”0” and REG_DATA Pin = ”0”. In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator. ● Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator.
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ST7538Q 5.8.1 Functional description Automatic Level Control (ALC) The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain: ● The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense.
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Functional description ST7538Q Voltage control loop formula R1 + R2 VR PK ≅ -------------------- ⋅ ( VCL TH ± VCL HYST ) R2 Table 10. Vout vs R1 & R2 resistors value Note: Vout (Vrms) Vout (dBµV) (R1+R2)/R2 R2 (KΩ) R1 (KΩ) 0.150 103.5 1.1 7.5 1.0 0.250 108.0 1.9 5.1 3.9 0.350 110.9 2.7 3.6 5.6 0.500 114.0 3.7 3.3 8.2 0.625 115.9 4.7 3.3 11.0 0.750 117.5 5.8 2.7 12.0 0.875 118.8 6.6 2.0 11.0 1.000 120.0 7.6 1.6 10.0 1.250 121.9 9.5 1.6 13.0 1.500 123.
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ST7538Q Functional description ● Integrated Power Line Interface (PLI) The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output (ATOP1). - Bridge Connection The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each individual Output. This topology virtually eliminates the even harmonics generation.
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Functional description ST7538Q Figure 17. PLI startup timing diagram RX/TX TALC TRXTX TST 4V ATOP2 0V STEP NUMBER 16 17 18 31 D03IN1408 5.9 Crystal oscillator ST7538Q integrates a inverter driver circuit to realize a 16MHz crystal oscillator. This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ESR of 40Ω.
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ST7538Q Functional description Figure 19. XIN waveform if an external oscillator is used 5.10 Control register The ST7538Q is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 11).
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Functional description ST7538Q Table 11. Control register functions Bits Function Value Selection Bit2 0 to 2 3 to 4 Frequencies Baud Rate 60 KHz 66 KHz 72 KHz 76 KHz 82.05 KHz 86 KHz 110 KHz 132.5 KHz 600 1,200 2,400 4,800 Note Default Bit1 Bit0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 4 Bit 3 0 0 1 1 0 1 0 1 132.5 kHz 2400 Bit 5 5 Deviation 0.5 1 0 1 0.
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ST7538Q Functional description Table 11.
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Functional description ST7538Q Table 11.
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ST7538Q 5.11 Functional description Detection method and Rx Sensitivity in UART mode When ST7538Q is running in UART mode (by forcing UART/SPI pin to “1”) the Control Register Function “Detection method” differs from SPI mode as indicated in the Table 12: Table 12.
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Auxiliary analog and digital functions ST7538Q 6 Auxiliary analog and digital functions 6.1 Band in use The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBµV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU line is forced High when a signal in band is detected. To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal. 6.
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ST7538Q Auxiliary analog and digital functions Figure 21. Reset and watchdog timing TRSTO TWO RSTO TRSTO TWM TWD WD D03IN1410 6.4 Zero crossing detection The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one.
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Auxiliary analog and digital functions 6.5 ST7538Q Output clock MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4) or can be disabled (off). The transition between one frequency and another is done only at the end of the ongoing cycle. 6.
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ST7538Q 6.11 Auxiliary analog and digital functions 5V and 3.3V voltage regulators and power good function ST7538Q has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50µA) and a current capability of 50mA. The regulator is protected against short circuitry events. The DVdd pin can act either as 3.3V Voltage Output or as Input Digital Supply.
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Auxiliary analog and digital functions 6.12 ST7538Q Power-up procedure To ensure ST7538Q proper power-Up sequence, PAVcc, AVdd and DVdd Supply has to fulfil the following rules: PAVcc rising slope must not exceed 100V/ms. When DVdd is below 5V/3.3V and AVdd is below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V. When AVdd and DVdd supplies are connected to VDC the above mentioned relation is guarantied if VDC load < 100mA and if the filtering capacitor on VDC < 100uF.
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HOST CONTROLLER 5V Supply for Host Controller Clock & Reset for Host Controller 12 11 43 8 4 5 3 1 15 9 7 36 42 14 35 30 13 10 28 20 N.C. DVSS 33 44 N.C. PAVSS RSTO MCLK 5 Lines Serial Interface REG/DATA CLR/T RX/TX TxD RxD CD/PD ZCOUT BU TOUT REGOK PG WD TEST1 TEST2 UART/SPI DVdd AVdd VDC 18 34 N.C. 17 DVSS 2 GND ST7538Q N.C.
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Package mechanical data 7 ST7538Q Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
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ST7538Q 8 Revision history Revision history Table 13. Revision history Date Revision 12-Jul-2006 1 Changes Initial release.
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ST7538Q Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.