Datasheet

ST72321Rx ST72321ARx ST72321Jx
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16-BIT TIMER (Cont’d)
Figure 42. Timer Block Diagram
MCU-PERIPHERAL INTERFACE
COUNTER
ALTERNATE
OUTPUT
COMPARE
REGISTER
OUTPUT COMPARE
EDGE DETECT
OVERFLOW
DETECT
CIRCUIT
1/2
1/4
1/8
8-bit
buffer
ST7 INTERNAL BUS
LATCH1
OCMP1
ICAP1
EXTCLK
f
CPU
TIMER INTERRUPT
ICF2ICF1
TIMD
0
0
OCF2OCF1 TOF
PWMOC1E
EXEDG
IEDG2CC0CC1
OC2E
OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE
ICAP2
LATCH2
OCMP2
8
8
8 low
16
8 high
16 16
16
16
(Control Register 1) CR1
(Control Register 2) CR2
(Control/Status Register)
6
16
8 8 8
88 8
high low high high high low low low
EXEDG
TIMER INTERNAL BUS
CIRCUIT1
EDGE DETECT
CIRCUIT2
CIRCUIT
1
OUTPUT
COMPARE
REGISTER
2
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
CC[1:0]
COUNTER
pin
pin
pin
pin
pin
REGISTER
REGISTER
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
(See note)
CSR