Datasheet

ST72321Rx ST72321ARx ST72321Jx
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 15. Main Clock Controller Register Map and Reset Values
70
000000BC1BC0
BC1 BC0 Beep mode with f
OSC2
=8MHz
00 Off
01 ~2-KHz
Output
Beep signal
~50% duty cycle
10 ~1-KHz
1 1 ~500-Hz
Address
(Hex.)
Register
Label
76543210
002Bh
SICSR
Reset Value
AVDS
0
AVDIE
0
AVDF
0
LVDRF
x000
WDGRF
x
002Ch
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh
MCCBCR
Reset Value000000
BC1
0
BC0
0