Datasheet

ST72321Rx ST72321ARx ST72321Jx
30/193
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
of the comparator output. This means it is generat-
ed when either one of these two events occur:
–V
EVD
rises up to V
IT+(EVD)
–V
EVD
falls down to V
IT-(EVD)
The EVD function is illustrated in Figure 17.
For more details, refer to the Electrical Character-
istics section.
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generate an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
V
EVD
V
IT+(EVD)
V
IT-(EVD)
AVDF 0 01
IF AVDIE = 1
V
hyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
Mode Description
WAIT
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
HALT The SICSR register is frozen.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
AVD event AVDF AVDIE Yes No