Datasheet

ST72321Rx ST72321ARx ST72321Jx
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RESET SEQUENCE MANAGER (Cont’d)
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET
pulse is shorter than
t
w(RSTL)out
(see short ext. Reset in Figure 14), the
signal on the RESET
pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 14). Starting from the external RE-
SET pulse recognition, the device RESET
pin acts
as an output that is pulled low during at least
t
w(RSTL)out
.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
DD
is over the minimum
level specified for the selected f
OSC
frequency.
(see “OPERATING CONDITIONS” on page 140)
A proper reset signal for a slow rising V
DD
supply
can generally be provided by an external RC net-
work connected to the RESET
pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in Figure 14.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET
pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 14. RESET Sequences
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
t
w(RSTL)out
RUN
t
h(RSTL)in
ACTIVE
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN RUN RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
t
w(RSTL)out
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
DELAY