Datasheet

ST72321Rx ST72321ARx ST72321Jx
17/193
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
0058h
to
006Fh
Reserved Area (24 Bytes)
0070h
0071h
0072h
ADC
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
PWM ART
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
007Eh
007Fh
Reserved Area (2 Bytes)
Address Block
Register
Label
Register Name
Reset
Status
Remarks