Datasheet

ST72321Rx ST72321ARx ST72321Jx
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12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
DD
,
f
CPU
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS
, SCK, MOSI, MISO).
Figure 92. SPI Slave Timing Diagram with CPHA=0
3)
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
4. Depends on f
CPU
. For example, if f
CPU
= 8 MHz, then t
CPU
= 1 / f
CPU
= 125 ns and t
su(SS)
= 175 ns.
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master
f
CPU
=8MHz
f
CPU
/128
0.0625
f
CPU
/4
2
MHz
Slave
f
CPU
=8MHz
0
f
CPU
/2
4
t
r(SCK)
t
f(SCK)
SPI clock rise and fall time see I/O port pin description
t
su(SS)
SS setup time
4)
Slave t
CPU
+ 50
ns
t
h(SS)
SS hold time Slave 120
t
w(SCKH)
t
w(SCKL)
SCK high and low time
Master
Slave
100
90
t
su(MI)
t
su(SI)
Data input setup time
Master
Slave
100
100
t
h(MI)
t
h(SI)
Data input hold time
Master
Slave
100
100
t
a(SO)
Data output access time Slave 0 120
t
dis(SO)
Data output disable time Slave 240
t
v(SO)
Data output valid time
Slave (after enable edge)
120
t
h(SO)
Data output hold time 0
t
v(MO)
Data output valid time
Master (after enable edge)
120
t
CPU
t
h(MO)
Data output hold time 0
SS
INPUT
SCK
INPUT
CPHA=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
v(SO)
t
a(SO)
t
su(SI)
t
h(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
seenote2
CPOL=0
CPOL=1
t
su(SS)
t
h(SS)
t
dis(SO)
t
h(SO)
see
note 2
BIT1 IN