Datasheet

ST72321Rx ST72321ARx ST72321Jx
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12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET
Pin
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
IO
current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET
pin. All short pulses applied on
the RESET pin with a duration below t
h(RSTL)in
can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Typ
Max Unit
V
IL
Input low level voltage
1)
0.16xV
DD
V
V
IH
Input high level voltage
1)
0.85xV
DD
V
hys
Schmitt trigger voltage hysteresis
2)
2.5
V
V
OL
Output low level voltage
3)
V
DD
=5V I
IO
=+2mA 0.2 0.5
I
IO
Input current on RESET pin 2 mA
R
ON
Weak pull-up equivalent resistor 20 30 120 kΩ
t
w(RSTL)out
Generated reset pulse duration
Stretch applied on
external pulse
042
6)
μs
Internal reset sources 20 30 42
6)
μs
t
h(RSTL)in
External reset pulse hold time
4)
2.5 μs
t
g(RSTL)in
Filtered glitch duration
5)
200 ns