Datasheet

ST72321Rx ST72321ARx ST72321Jx
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12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Figure 81. Unused I/Os configured as input Figure 82. Typical I
PU
vs. V
DD
with V
IN
=V
SS
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
IN
maximum must be respected, otherwise refer to I
INJ(PIN)
specifica-
tion. A positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. Refer to section 12.2.2
on page 139 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 81). Static
peak current value taken at a fixed V
IN
value, based on design simulation and technology characteristics, not tested in
production. This value depends on V
DD
and temperature values.
5. The R
PU
pull-up equivalent resistor is based on a resistive transistor (corresponding I
PU
current characteristics de-
scribed in Figure 82).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage
1)
CMOS ports
0.3xV
DD
VV
IH
Input high level voltage
1)
0.7xV
DD
V
hys
Schmitt trigger voltage hysteresis
2)
0.7
I
INJ(PIN)
3)
Injected Current on PC6 (Flash de-
vices only)
V
DD
=5V
0+4
mA
Injected Current on an I/O pin ± 4
ΣI
INJ(PIN)
3)
Total injected current (sum of all I/O
and control pins)
± 25
I
L
Input leakage current V
SS
≤ V
IN
≤ V
DD
±1
μA
I
S
Static current consumption Floating input mode
4)
400
R
PU
Weak pull-up equivalent resistor
5)
V
IN
=V
SS
V
DD
=5V 50 120 250 kΩ
C
IO
I/O pin capacitance 5 pF
t
f(IO)out
Output high to low level fall time
1)
C
L
=50pF
Between 10% and 90%
25
ns
t
r(IO)out
Output low to high level rise time
1)
25
t
w(IT)in
External interrupt pulse time
6)
1t
CPU
10kΩ
ST7XXX
10kΩ
UNUSED I/O PORT
ST7XXX
V
DD
Note: I/O can be left unconnected if it is configured as output
greater EMC robustness and lower cost.
(0 or 1) by the software. This has the advantage of
UNUSED I/O PORT
0
10
20
30
40
50
60
70
80
90
22.533.5 44.555.56
Vdd(V)
Ipu(uA)
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C