Datasheet

ST72321Rx ST72321ARx ST72321Jx
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CLOCK CHARACTERISTICS (Cont’d)
Note:
1. Data based on characterization results.
12.5.5 PLL Characteristics
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 80 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
Figure 80. Integrated PLL Jitter vs signal frequency
1
Note 1: Measurement conditions: f
CPU
= 8MHz.
Symbol Parameter Conditions Min Typ Max Unit
f
OSC
PLL input frequency range 2 4 MHz
Δ f
CPU
/ f
CPU
Instantaneous PLL jitter
1)
f
OSC
= 4 MHz. 1.0 2.5 %
f
OSC
= 2 MHz. 2.5 4.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz
Application Frequency
+/-Jitter (%)