Datasheet

ST72321Rx ST72321ARx ST72321Jx
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
ADC
= f
CPU
/4
1: f
ADC
= f
CPU
/2
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
70
EOC SPEED ADON 0 CH3 CH2 CH1 CH0
Channel Pin* CH3 CH2 CH1 CH0
AIN0 0000
AIN1 0001
AIN2 0010
AIN3 0011
AIN4 0100
AIN5 0101
AIN6 0110
AIN7 0111
AIN8 1000
AIN9 1001
AIN10 1010
AIN11 1011
AIN12 1100
AIN13 1101
AIN14 1110
AIN15 1111
70
D9 D8 D7 D6 D5 D4 D3 D2
70
000000D1D0