Datasheet

ST72321Rx ST72321ARx ST72321Jx
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C BUS INTERFACE (Cont’d)
Figure 66. Transfer Sequencing
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master transmitter
10-bit Master receiver:
S Address A Data1 A Data2 A
.....
DataN A P
EV1 EV2 EV2 EV2 EV4
S Address A Data1 A Data2 A
.....
DataN NA P
EV1 EV3 EV3 EV3 EV3-1 EV4
S Address A Data1 A Data2 A
.....
DataN NA P
EV5 EV6 EV7 EV7 EV7
S Address A Data1 A Data2 A
.....
DataN A P
EV5 EV6 EV8 EV8 EV8 EV8
S Header A Address A Data1 A
.....
DataN A P
EV1 EV2 EV2 EV4
S
r
Header A Data1 A
....
.
DataN A P
EV1 EV3 EV3 EV3-1 EV4
S Header A Address A Data1 A
.....
DataN A P
EV5 EV9 EV6 EV8 EV8 EV8
S
r
Header A Data1 A
.....
DataN A P
EV5 EV6 EV7 EV7