Datasheet

ST72321Rx ST72321ARx ST72321Jx
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 60. SCI Block Diagram
WAKE
UP
UNIT
RECEIVER
CONTROL
SR
TRANSMIT
CONTROL
TDRE TC RDRF IDLE OR NF FE PE
SCI
CONTROL
INTERRUPT
CR1
R8 T8 SCID M WAKE PCE PS PIE
Received Data Register (RDR)
Received Shift Register
Read
Transmit Data Register (TDR)
Transmit Shift Register
Write
RDI
TDO
(DATA REGISTER) DR
TRANSMITTER
CLOCK
RECEIVER
CLOCK
RECEIVER RATE
TRANSMITTER RATE
BRR
SCP1
f
CPU
CONTROL
CONTROL
SCP0
SCT2
SCT1 SCT0 SCR2
SCR1SCR0
/PR
/16
CONVENTIONAL BAUD RATE GENERATOR
SBKRWURETEILIERIETCIETIE
CR2