Datasheet

DocID023654 Rev 2 19/27
ST1S41 Application information
Equation 26
where T
A
is the ambient temperature and P
TOT
is the sum of the power losses just seen.
Rth
JA
is the equivalent thermal resistance junction-to-ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth
JA
measured on the demonstration board described in the following
paragraph is about 40 °C/W for the VFQFPN and HSOP packages.
Figure 7. Switching losses
6.5 Layout considerations
The PC board layout of switching DC-DC regulator is very important to minimize the noise
injected in high impedance nodes, to reduce interference generated by the high switching
current loops and to optimize the reliability of the device.
In order to avoid EMC problems, the high switching current loops must be as short as
possible. In the buck converter there are two high switching current loops: during the on-
time, the pulsed current flows through the input capacitor, the high-side power switch, the
inductor and the output capacitor; during the off-time, through the low-side power switch, the
inductor and the output capacitor.
T
J
T
A
Rth
JA
P
TOT
⋅+=
V
SW
I
SW,HS
V
IN
V
DS,HS
P
COND,HS
P
COND,LS
P
SW
T
FALL
T
RISE
AM15064v1