ST1S41 4 A step-down switching regulator Datasheet - production data Applications • μP/ASIC/DSP/FPGA core and I/O supplies • Point of load for: STB, TVs, DVD VFQFPN8 4x4 • Optical storage, hard disk drive, printers, audio/graphic cards HSOP8 Description The ST1S41 is an internally compensated 850 kHz fixed-frequency PWM synchronous stepdown regulator. The ST1S41 operates from 4.0 V to 18 V input, while it regulates an output voltage as low as 0.8 V and up to VIN. Features • 4 A output current • 4.
Contents ST1S41 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . .
ST1S41 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) VINA 1 8 PGND 9 9 EN EN 2 6 SW FB 3 7 VINSW GND 4 5 NC NC VFQFPN 1.2 HSOP8 AM15059v1 Pin description Table 1. Pin description N. Type Description 1 VINA 2 EN Enable input. With EN higher than 1.2 V the device in ON and with EN lower than 0.4 V the device is OFF (ST1S41Ixx). 3 FB Feedback input.
Maximum ratings 2 ST1S41 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Power input voltage -0.3 to 20 VINA Input voltage -0.3 to 20 VEN Enable voltage VSW Output switching voltage VPG Power Good -0.3 to VIN VFB Feedback voltage -0.3 to 2.5 IFB FB current VINSW 3 Value -0.3 to VINA Unit V -1 to VIN -1 to +1 mA 2.
ST1S41 4 Electrical characteristics Electrical characteristics TJ = 25 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. Max. VIN Operating input voltage range (1) VINON Turn-on VCC threshold (1) 2.9 VINHYS Threshold hysteresis (1) 0.250 RDSON-P High-side switch onresistance ISW=750 mA 95 mΩ RDSON-N Low-side switch onresistance ISW=750 mA 69 mΩ ILIM Maximum limiting current 4 (2) 18 5.
Electrical characteristics ST1S41 Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Protection TSHDN Thermal shutdown 150 Hystereris 15 °C 1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design.
ST1S41 5 Functional description Functional description The ST1S41 is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the on and off-time of the power switch. The main internal blocks are shown in the block diagram in Figure 3.
Functional description 5.1 ST1S41 Internal soft-start The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically. The soft-start is performed by ramping the non-inverting input (VREF) of the error amplifier from 0 V to 0.8 V in around 1 ms. 5.2 Error amplifier and control loop stability The error amplifier compares the FB pin voltage with the internal 0.
ST1S41 Functional description Figure 4. Block diagram of the loop for the small signal analysis VIN Slope G CO( s ) Compensation High side Switch L Current sense Logic and Driver Low side Switch VOUT G DIV(s ) Cout PWM comparator 0.8V R1 VC Rc V FB Error Amp R2 Cc G EA( s ) AM15061v1 Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, GCO(s); 2. from output (Vout) to FB pin, GDIV(s); 3.
Functional description ST1S41 Equation 3 m C ⋅ ( 1 – D ) – 0.
ST1S41 Functional description The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. Figure 5 shows the small signal model of the error amplifier with the internal compensation network. Figure 5. Small signal model for the error amplifier VFB Ro Vd Co Gm*Vd Rc Cp Cc VREF AM15062v1 RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected.
Functional description ST1S41 So closing the loop, the loop gain GLOOP(s) is: Equation 14 G LOOP ( s ) = G CO ( s ) ⋅ G DIV ( s ) ⋅ G EA ( s ) Example: VIN=12 V, VOUT=1.2 V, Iomax=4 A, L=1.5 uH, Cout=47 uF (MLCC), R1=10 kΩ, R2=20 kΩ (see Section 6.2 and Section 6.3 for inductor and output capacitor selection guidelines). The module and phase bode plot are reported in Figure 6. The bandwidth is 100 kHz and the phase margin is 45 degrees.
ST1S41 Functional description Figure 6. Module and phase bode plot 5.3 Overcurrent protection The ST1S41 implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high-side power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high-side is immediately turned off and the low-side conducts the inductor current for the rest of the clock period and the following high-side cycle is disabled.
Functional description ST1S41 The current foldback is disabled during the startup to allow the Vout to start up properly in case of a big output capacitor requiring high extra current to be charged. A further mechanism is protecting the device in case of short-circuit on the output and high input voltage. A further threshold (OCP2, 1 A higher than OCP1) is compared to the inductor current. If the inductor current exceeds OCP2, the device stops switching and it restarts with a soft-start cycle. 5.
ST1S41 Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
Application information ST1S41 Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order of 1% of VINMAX. In Table 6 some multi-layer ceramic capacitors suitable for this device are reported. Table 6.
ST1S41 Application information So, if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table 7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (μH) Saturation current (A) XAL5030/6030 2.2 to 4.7 6.7 to 15.5 MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.
Application information ST1S41 Table 8. Output capacitors (continued) Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) ECJ 10 to 22 6.3 <5 EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 <5 PANASONIC 6.4 Thermal dissipation The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C.
ST1S41 Application information Equation 26 T J = T A + Rth JA ⋅ P TOT where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction-to-ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat.
Application information ST1S41 The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current. In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the VINA pin to the input must be derived from VINSW.
ST1S41 7 Typical characteristics Typical characteristics Figure 10. Efficiency vs. IOUT@Vin=12 V 100 90 90 80 80 Efficiency [%] 100 70 Vin=5V 60 70 Vin=12V Vo=5V 60 Vo=3.3V Vo=3.3V Vo=1.8V 50 50 Vo=1.2V 40 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Iout [A] 40 0.00 4.50 0.50 1.00 1.50 2.00 Figure 11. Start at full load 4 A 2.50 3.00 3.50 Iout [A] AM15066v1 4.00 4.50 AM15067v1 Figure 12. Efficiency vs.
Typical characteristics ST1S41 Figure 13.
ST1S41 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. VFQFPN8 (4x4x1.08 mm) mechanical data mm Dim. Min. A 0.80 Typ. Max. 0.90 1.00 A1 0.02 0.05 A3 0.20 b 0.23 0.30 0.38 D 3.90 4.00 4.
Package mechanical data ST1S41 Table 10. HSOP8 mechanical data mm Dim. Min. Typ. A 1.70 A1 0.00 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 0.15 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8 ccc 0.10 Figure 15. HSOP8 package dimensions 24/27 Max.
ST1S41 9 Ordering information Ordering information Table 11.
Revision history 10 ST1S41 Revision history Table 12. Document revision history 26/27 Date Revision Changes 14-Sep-2012 1 Initial release. 24-Apr-2013 2 Updated Table 4: Electrical characteristics and Table 11: Ordering information.
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