Datasheet

DocID17928 Rev 5 7/29

ST1S40 Functional description

5 Functional description

The ST1S40 device is based on a “peak current mode”, constant frequency control. The

output voltage V

OUT

is sensed by the feedback pin (FB) compared to an internal reference

(0.8 V) providing an error signal that, compared to the output of the current sense amplifier,

controls the ON and OFF time of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

 A fully integrated oscillator that provides the internal clock and the ramp for the slope

compensation avoiding sub-harmonic instability

 The soft-start circuitry to limit inrush current during the startup phase

 The transconductance error amplifier with integrated compensation network

 The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switches

 The drivers for embedded P-channel and N-channel Power MOSFET switches

 The high side current sensing block

 The low side current sense to implement diode emulation

 A voltage monitor circuitry (UVLO) that checks the input and internal voltages

 A thermal shutdown block, to prevent thermal run-away.

Figure 3. Block diagram

OSC

E/A

DRIVER

DMD

OTP

MOSFET

CONTROL

LOGIC

REGULATOR

SHUT-DOWN

I_SENSE

COMP

OCP

REF

0.8V

SOFTSTART

Vsum

OCP

UVLO

Vdrv_p

Vdrv_n

I2V

SENSE

VINA VINSW

GNDPGNDAENFB