Datasheet

DocID17928 Rev 5 17/29
ST1S40 Application information
29
6.4 Thermal dissipation
The thermal design is important in order to prevent thermal shutdown of the device if
junction temperature goes above 150 °C. The three different sources of losses within the
device are:
a) conduction losses due to the ON resistance of high side switch (R
HS
) and low side
switch (R
LS
); these are equal to:
Equation 22
where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between V
OUT
and V
IN
, but is actually slightly higher to compensate the losses of
the regulator.
b) switching losses due to high side Power MOSFET turn ON and OFF; these can be
calculated as:
Equation 23
where T
RISE
and T
FALL
are the overlap times of the voltage across the high side power
switch (V
DS
) and the current flowing into it during turn ON and turn OFF phases, as shown
in Figure 7. T
SW
is the equivalent switching time. For this device the typical value for the
equivalent switching time is 20 ns.
c) Quiescent current losses, calculated as:
Equation 24
where I
Q
is the quiescent current (I
Q
= 2.5 mA maximum).
The junction temperature T
J
can be calculated as:
Equation 25
where T
A
is the ambient temperature and P
TOT
is the sum of the power losses just seen.
Rth
JA
is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth
JA
measured on the demonstration board described in the following
paragraph is about 40 °C/W for the VFQFPN and HSOP packages and about 55 °C/W for
the SO8-BW package.
P
COND
R
HS
I
OUT
2
DR
LS
I
OUT
2
1D–+=
P
SW
V
IN
I
OUT
T
RISE
T
FALL
+
2
------------------------------------------ - Fsw  V
IN
I
OUT
T
SW
F
SW
==
P
Q
V
IN
I
Q
=
T
J
T
A
Rth
JA
P
TOT
+=