ST1S40 3 A DC step-down switching regulator Datasheet - production data Applications P/ASIC/DSP/FPGA core and I/O supplies Point of load for: STB, TVs, DVD HSOP-8 Optical storage, hard disk drive, printers, audio/graphic cards SO8 VFQFPN 4 x 4 Description Features The ST1S40 device is an internally compensated 850 kHz fixed-frequency PWM synchronous stepdown regulator. The ST1S40 operates from 4.0 V to 18 V input, while it regulates an output voltage as low as 0.8 V and up to VIN.
Contents ST1S40 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . .
ST1S40 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) VINA 1 EN 2 FB 3 GND 4 9 VINA 1 SW EN 2 6 VINSW FB 3 5 NC GND 4 8 PGND 7 PGND 7 SW 6 VINSW 5 NC 8 SW VINSW PGND HSOP-8 HSOP8 VFQFPN 1.2 9 1 8 GND VINA EN AGND 4 5 FB SO8-BW Pin description Table 1. Pin description No. VFQFPN S08-BW and HSOP-8 Type Description 1 3 VINA 2 4 EN Enable input. With EN higher than 1.
Maximum ratings 2 ST1S40 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Power input voltage -0.3 to 20 VINA Input voltage -0.3 to 20 VEN Enable voltage VINSW 3 Parameter -0.3 to VINA VSW Output switching voltage VFB Feedback voltage IFB FB current -1 to VIN Unit V -2 V to -1 V for 50 nsec -0.3 to 2.5 -1 to +1 mA 2.25 (HSOP-8/DFN4x4); 1.
ST1S40 4 Electrical characteristics Electrical characteristics TJ = 25 °C, VCC= 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. VIN Operating input voltage range (1) VINON Turn-on VCC threshold (1) 2.9 VINHYS Threshold hysteresis (1) 0.250 RDSON-P High side switch ON resistance ISW = 750 mA 95 RDSON-N Low side switch ON resistance ISW = 750 mA 69 ILIM Maximum limiting current (2) 4 Max. 18 4.
Electrical characteristics ST1S40 Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Soft start TSS Soft-start duration 1 ms Protection TSHDN Thermal shutdown 150 Hysteresis 15 °C 1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design.
ST1S40 5 Functional description Functional description The ST1S40 device is based on a “peak current mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3.
Functional description 5.1 ST1S40 Internal soft-start The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and causes the output voltage to increase monothonically. The soft-start is performed by ramping the non-inverting input (VREF) of the error amplifier from 0 V to 0.8 V in around 1 ms. 5.2 Error amplifier and control loop stability The error amplifier compares the FB pin voltage with the internal 0.
ST1S40 Functional description Figure 4 shows the simple small signal model for the peak current mode control loop. Figure 4. Block diagram of the loop for the small signal analysis VIN GCO(s) Slope Compensation High side Switch L Current sense Logic And Driver VOUT GDIV (s) Cout Low side Switch PWM comparator 0.8V R1 VC Rc VFB Error Amp R2 Cc G EA(s) Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, GCO(s) 2.
Functional description ST1S40 Equation 3 m C 1 – D – 0.5 1 p = -------------------------------------- + --------------------------------------------L C OUT f SW R LOAD C OUT where: Equation 4 Se m C = 1 + -----Sn S = V f pp SW e V IN – V OUT S = ----------------------------- Ri n L Sn represents the ON time slope of the sensed inductor current, Se the slope of the external ramp (VPP peak-to-peak amplitude 1.
ST1S40 Functional description Figure 5. Small signal model for the error amplifier 9 )% 5R 9G &R *P 9G 5F &S &F 95() RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability and can be neglected.
Functional description ST1S40 so by closing the loop, the loop gain GLOOP(s) is: Equation 13 G LOOP s = G CO s G DIV s G EA s Example: VIN = 12 V, VOUT = 1.2 V, Iomax = 3 A, L = 1.5 µH, Cout = 47 µF (MLCC), R1 = 10 k, R2 = 20 k(see Section 6.2 and Section 6.3 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure 6. The bandwidth is 100 kHz and the phase margin is 45 degrees. Figure 6.
ST1S40 5.3 Functional description Overcurrent protection The ST1S40 device implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high side Power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high side is immediately turned off and the low side conducts the inductor current for the rest of the clock period.
Application information ST1S40 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
ST1S40 Application information In Table 6 some multi layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Murata TDK Series Cap value (F) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise.
Application information ST1S40 In Table 7 below some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (H) Saturation current (A) XPL7030 2.2 to 4.7 6.8 to 10.5 MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.5 WE-HC/HCA 3.3 to 4.7 7 to 11 WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4 WE-PD type L 10 5.6 RLF7030T 2.2 to 4.7 4 to 6 Coilcraft Wurth TDK 6.
ST1S40 6.4 Application information Thermal dissipation The thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the ON resistance of high side switch (RHS) and low side switch (RLS); these are equal to: Equation 22 2 2 P COND = R HS I OUT D + R LS I OUT 1 – D where D is the duty cycle of the application.
Application information ST1S40 Figure 7. Switching losses VIN VSW ISW,HS VDS,HS PSW PCOND,HS PCOND,LS TFALL 6.5 TRISE Layout consideration The PC board layout of switching DC-DC regulator is very important in order to minimize the noise injected in high impedance nodes, to reduce interferences generated by the high switching current loops, and to optimize the reliability of the device. In order to avoid EMC problems, the high switching current loops must be as short as possible.
ST1S40 Application information Figure 8.
Demonstration board 7 ST1S40 Demonstration board Figure 9. Demonstration boards schematic Table 9. Component list 20/29 Reference Part number Description Manufacturer U1 ST1S40 L1 DRA74 3R3 3.3 µH, Isat = 5.4 A Coiltronics C1 C3225X7RE106K 10 µF 25 V X7R TDK C2 C3225X7R1C226M 22 µF 16 V X7R TDK STMicroelectronics® C3 1 µF 25 V X7R C4 NC R1 62.
ST1S40 Demonstration board Figure 10. Demonstration board PCB top and bottom: HSOP-8 package Figure 11. Demonstration board PCB top and bottom: VFQFPN package Figure 12.
Typical characteristics 8 ST1S40 Typical characteristics Figure 13. Efficiency vs. IOUT Figure 14. Efficiency vs. IOUT 90 100 85 90 80 75 Efficiency [%] Efficiency [%] 80 70 Vin=5V 60 65 60 Vin=12V 55 Vo=1.8V Vo=3.3V 50 70 50 Vo=1.2V Vo=1.8V 45 Vo=1.2V 40 40 0.00 0.50 1.00 1.50 2.00 2.50 3.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Iout [A] Iout [A] Figure 15. Efficiency vs. IOUT Figure 16. Overcurrent protection 100 90 Efficiency [%] 80 70 Vin=12V Vo=5V 60 Vo=3.
ST1S40 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Package information ST1S40 Figure 19. VFQFPN8 (4 x 4 x 1.0 mm) package outline % Table 10. VFQFPN8 (4 x 4 x 1.0 mm) package mechanical data Dimensions Symbol mm Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A3 0.20 A 0.0079 b 0.23 0.30 0.38 0.009 0.0117 0.0149 D 3.90 4.00 4.10 0.153 0.157 0.161 D2 2.82 3.00 3.23 0.111 0.118 0.127 E 3.90 4.00 4.10 0.153 0.157 0.161 E2 2.05 2.20 2.30 0.081 0.087 0.
ST1S40 Package information Figure 20. SO8-BW package outline K [ & 6HDWLQJ 3ODQH GGG & $ $ $ H % PP *DJH 3ODQH N / ' ( + & Table 11. SO8-BW package mechanical data Dimensions Symbol mm Min. Typ. inch Max. Min. Typ. Max. A 135 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.001 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.01 (1) 4.80 5.00 0.1890 E 3.80 4.00 0.15 D e 1.27 0.1929 0.1969 0.157 0.050 H 5.
Package information ST1S40 Figure 21.
ST1S40 Package information Table 12. HSOP-8 package mechanical data Dimensions Symbol mm Min. Typ. A inch Max. Min. Typ. 1.70 Max. 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 0.1929 0.1969 E 5.80 6.00 6.20 0.2283 0.2362 0.2441 E1 3.80 3.90 4.00 0.1496 0.1535 0.1575 e 0.150 0.00 0.0059 0.0492 1.27 0.0500 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k 0.00 8.00 0.3150 0.10 0.
Order codes 10 ST1S40 Order codes Table 13. Ordering information 11 Order codes Package ST1S40IPUR VFQFPN 4 x 4 8L ST1S40IPHR HSOP-8 ST1S40IDR SO8-BW Function Enable Revision history Table 14. Document revision history Date Revision 15-Dec-2010 1 First release 04-Mar-2011 2 Updated: Table 1, Table 2, Table 3 and Table 13.
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