Datasheet

DocID023280 Rev 3 17/28
ST1S15 Application Information
8.3 Layout guidelines
Due to the high switching frequency and peak current, the layout is an important design step
for all switching power supplies. If the layout is not done carefully, important parameters
such as stability, efficiency, line and load regulation and output voltage ripple may be
compromised.
Short, wide traces must be implemented for main current and for power ground paths. The
input capacitor must be placed as close as possible to the device pin as well as the inductor
and output capacitor.
The FEEDBACK pin (FB) is a high impedance node, so the interference can be minimized
by placing the routing of the feedback node as far as possible from the high current paths.
A common ground node minimizes ground noise.
The exposed pad of the DFN package must be connected to the common ground node.
Figure 24. DFN layout recommended (not to scale)
Figure 25. Flip-Chip layout recommended (not to scale)
AM11908v1
V
IN
MODE
GND
C
IN
C
OUT
EN
L
EN
V
OUT
AM11910v1
EN
V
IN
MODE
GND
L
C
IN
C
OUT
V
OUT