Datasheet

Closing the loop ST1S14
20/46 DocID17977 Rev 2
where:
6.4 Total loop gain
In summary, the open loop gain can be expressed as:
Equation 15
Example: V
IN
= 12 V, V
OUT
= 3.3 V, R
OUT
= 2 Ω.
The resistor divider is R
1
=5.6 K, R
2
=3.3 K.
C
R1
=150 nF implements a leading network (f
Z
=190 kHz, f
P
=510 kHz).
Selecting L = 8.2 µH, C
OUT
= 100 µF, and ESR = 75 mΩ, the gain and phase bode
diagrams are plotted respectively in Figure 12 and 13 over input voltage range (V
IN
=6
V to 48 V, I
OUT
=3 A).
Figure 12. Module plot
G
DIV
s()
R
2
R
1
R
2
+
--------------------
1sR
1
C
R1
⋅⋅+()
1s
R
1
R
2
⋅
R
1
R
2
+
---------------------
C
R1
⋅⋅+
⎝⎠
⎛⎞
-----------------------------------------------------------------
⋅=
f
Z
1
2 π R
1
C
R1
⋅⋅ ⋅
----------------------------------------------
=
f
P
1
2 π
R
1
R
2
⋅
R
1
R
2
+
---------------------
C
R1
⋅⋅ ⋅
------------------------------------------------------------ -=
f
Z
f
P
<
Gs() G
DIV
s() G
CO
s() A
0
s()⋅⋅=
$09