Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Application circuit
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Application information
- 5.1 Description
- 5.2 External components selection
- 5.3 Output capacitor (VOUT > 2.5 V)
- 5.4 Output capacitor (0.8 V < VOUT < 2.5 V)
- 5.5 Output voltage selection
- 5.6 Inductor (VOUT > 2.5 V)
- 5.7 Inductor (0.8 V < VOUT < 2.5 V)
- 5.8 Function operation
- 6 Layout considerations
- 7 Diagram
- 8 Typical performance characteristics
- Figure 9. Voltage feedback vs. temperature
- Figure 10. Oscillator frequency vs. temperature
- Figure 11. Max duty cycle vs. temperature
- Figure 12. Inhibit threshold vs. temperature
- Figure 13. Reference line regulation vs. temperature
- Figure 14. Reference load regulation vs. temperature
- Figure 15. ON mode quiescent current vs. temperature
- Figure 16. Shutdown mode quiescent current vs. temperature
- Figure 17. PMOS ON resistance vs. temperature
- Figure 18. NMOS ON resistance vs. temperature
- Figure 19. Efficiency vs. temperature
- Figure 20. Efficiency vs. output current@Vout = 5 V
- Figure 21. Efficiency vs. output current@Vout = 3.3 V
- Figure 22. Efficiency vs. output current@Vout = 12 V
- 9 Package mechanical data
- Table 6. Power SO-8 (exposed pad) mechanical data
- Figure 23. Power SO-8 (exposed pad) dimensions
- Figure 24. Power SO-8 (exposed pad) recommended footprint
- Table 7. Power SO-8 (exposed pad) tape and reel mechanical data
- Figure 25. Power SO-8 (exposed pad) tape and reel dimensions
- Table 8. DFN8 (4X4) mechanical data
- Figure 26. DFN8 (4x4) dimensions
- Table 9. DFN8 (4x4)tape and reel mechanical data
- Figure 27. DFN8 (4x4)tape and reel dimensions
- 10 Revision history

Layout considerations ST1S10
16/29 Doc ID 13844 Rev 5
6 Layout considerations
Layout is an important step in design for all switching power supplies.
High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB
layout. Care must be taken in board layout to get device performance, otherwise the
regulator could show poor line and load regulation, stability issues as well as EMI problems.
It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths.
The input capacitor must be placed as close as possible to the IC pins as well as the
inductor and output capacitor. Use a common ground node for power ground and a different
one for control ground (AGND) to minimize the effects of ground noise. Connect these
ground nodes together underneath the device and make sure that small signal components
returning to the AGND pin and do not share the high current path of C
IN
and C
OUT
.
The feedback voltage sense line (V
FB
) should be connected right to the output capacitor and
routed away from noisy components and traces (e.g., SW line). Its trace should be
minimized and shielded by a guard-ring connected to the ground.
Figure 6. PCB layout suggestion
V
FB
guard-ring
Input capacitor C1 must be placed
as close as possible to the IC
pins as well as the inductor L1
and output capacitor C2
Vias from thermal pad
to bottom layer
39mm
47mm
CN1=Input power supply
CN2=Enable/Disable
CN3=Input sync.
CN4=V
OUT
V
FB
guard-ring
Input capacitor C1 must be placed
as close as possible to the IC
pins as well as the inductor L1
and output capacitor C2
Vias from thermal pad
to bottom layer
39mm
47mm
CN1=Input power supply
CN2=Enable/Disable
CN3=Input sync.
CN4=V
OUT