Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Application circuit
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Application information
- 5.1 Description
- 5.2 External components selection
- 5.3 Output capacitor (VOUT > 2.5 V)
- 5.4 Output capacitor (0.8 V < VOUT < 2.5 V)
- 5.5 Output voltage selection
- 5.6 Inductor (VOUT > 2.5 V)
- 5.7 Inductor (0.8 V < VOUT < 2.5 V)
- 5.8 Function operation
- 6 Layout considerations
- 7 Diagram
- 8 Typical performance characteristics
- Figure 9. Voltage feedback vs. temperature
- Figure 10. Oscillator frequency vs. temperature
- Figure 11. Max duty cycle vs. temperature
- Figure 12. Inhibit threshold vs. temperature
- Figure 13. Reference line regulation vs. temperature
- Figure 14. Reference load regulation vs. temperature
- Figure 15. ON mode quiescent current vs. temperature
- Figure 16. Shutdown mode quiescent current vs. temperature
- Figure 17. PMOS ON resistance vs. temperature
- Figure 18. NMOS ON resistance vs. temperature
- Figure 19. Efficiency vs. temperature
- Figure 20. Efficiency vs. output current@Vout = 5 V
- Figure 21. Efficiency vs. output current@Vout = 3.3 V
- Figure 22. Efficiency vs. output current@Vout = 12 V
- 9 Package mechanical data
- Table 6. Power SO-8 (exposed pad) mechanical data
- Figure 23. Power SO-8 (exposed pad) dimensions
- Figure 24. Power SO-8 (exposed pad) recommended footprint
- Table 7. Power SO-8 (exposed pad) tape and reel mechanical data
- Figure 25. Power SO-8 (exposed pad) tape and reel dimensions
- Table 8. DFN8 (4X4) mechanical data
- Figure 26. DFN8 (4x4) dimensions
- Table 9. DFN8 (4x4)tape and reel mechanical data
- Figure 27. DFN8 (4x4)tape and reel dimensions
- 10 Revision history

ST1S10 Application information
Doc ID 13844 Rev 5 15/29
(*) see OCP and SCP descriptions for C2 and C4 selection.
Figure 3. Application schematic for heavy capacitive load
ST1S10
12V
L1
3.3µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
4.7µF
C2(*)
22µF
5V – 3A
C4 (*)
4.7nF
C
LOAD
LOAD
Output Load
ST1S10
12V
L1
3.3µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
4.7µF
C2(*)
22µF
5V – 3A5V – 3A
C4 (*)
4.7nF
C
LOAD
C
LOAD
LOAD
Output Load
Figure 4. Application schematic for low output voltage (V
OUT
< 2.5 V) and 2.5 V < V
IN
< 8 V
ST1S10
VIN<8V
L1
2.2µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
0.1µF
C2
2x22µF
0.8V<VOUT<2.5V
ST1S10
VIN<8V
L1
2.2µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
0.1µF
C2
2x22µF
0.8V<VOUT<2.5V
Figure 5. Application schematic for low output voltage (V
OUT
< 2.5 V) and 8 V < V
IN
< 16 V
ST1S10
8V<VIN<16V
L1
2.2µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
4.7µF
C2
2x22µF
0.8V<VOUT<2.5V
+
C5
100µF
Electrolytic
ESR<0.1Ohm
ST1S10
8V<VIN<16V
L1
2.2µH
C1
10µF
SW
FB
VIN_SW
SYNC
EN
R1
R2
VIN_A
AGND
PGND
C3
4.7µF
C2
2x22µF
0.8V<VOUT<2.5V
+
C5
100µF
Electrolytic
ESR<0.1Ohm