Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Application circuit
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Application information
- 5.1 Description
- 5.2 External components selection
- 5.3 Output capacitor (VOUT > 2.5 V)
- 5.4 Output capacitor (0.8 V < VOUT < 2.5 V)
- 5.5 Output voltage selection
- 5.6 Inductor (VOUT > 2.5 V)
- 5.7 Inductor (0.8 V < VOUT < 2.5 V)
- 5.8 Function operation
- 6 Layout considerations
- 7 Diagram
- 8 Typical performance characteristics
- Figure 9. Voltage feedback vs. temperature
- Figure 10. Oscillator frequency vs. temperature
- Figure 11. Max duty cycle vs. temperature
- Figure 12. Inhibit threshold vs. temperature
- Figure 13. Reference line regulation vs. temperature
- Figure 14. Reference load regulation vs. temperature
- Figure 15. ON mode quiescent current vs. temperature
- Figure 16. Shutdown mode quiescent current vs. temperature
- Figure 17. PMOS ON resistance vs. temperature
- Figure 18. NMOS ON resistance vs. temperature
- Figure 19. Efficiency vs. temperature
- Figure 20. Efficiency vs. output current@Vout = 5 V
- Figure 21. Efficiency vs. output current@Vout = 3.3 V
- Figure 22. Efficiency vs. output current@Vout = 12 V
- 9 Package mechanical data
- Table 6. Power SO-8 (exposed pad) mechanical data
- Figure 23. Power SO-8 (exposed pad) dimensions
- Figure 24. Power SO-8 (exposed pad) recommended footprint
- Table 7. Power SO-8 (exposed pad) tape and reel mechanical data
- Figure 25. Power SO-8 (exposed pad) tape and reel dimensions
- Table 8. DFN8 (4X4) mechanical data
- Figure 26. DFN8 (4x4) dimensions
- Table 9. DFN8 (4x4)tape and reel mechanical data
- Figure 27. DFN8 (4x4)tape and reel dimensions
- 10 Revision history

Application information ST1S10
14/29 Doc ID 13844 Rev 5
MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,
this pin must be connected to ground with a path as short as possible to avoid any possible
noise injected in the SYNC internal circuitry.
5.8.2 Inhibit function
The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically
reducing the current consumption down to less than 6 µA. When the inhibit feature is not
used, this pin must be tied to V
IN
to keep the regulator output ON at all times. To ensure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section under V
INH
.
Any slew rate can be used to drive the inhibit pin.
5.8.3 OCP (overcurrent protection)
The ST1S10 DC-DC converter is equipped with a switch overcurrent protection. In order to
provide protection for the application and the internal power switches and bonding wires, the
device goes into a shutdown state if the switch current limit is reached and is kept in this
condition for the T
OFF
period (T
OFF(OCP)
= 135 µs typ.) and turns on again for the T
ON
period
(T
ON(OCP)
= 22 µs typ.) under typical application conditions. This operation is repeated cycle
by cycle. Normal operation is resumed when no over-current is detected.
5.8.4 SCP (short circuit protection)
In order to protect the entire application and reduce the total power dissipation during an
overload or an output short circuit condition, the device is equipped with dynamic short
circuit protection which works by internally monitoring the V
FB
(feedback voltage).
In the event of an overload or output short circuit, if the V
OUT
voltage is reduced causing the
feedback voltage (V
FB
) to drop below 0.3 V (typ.), the device goes into shutdown for the
T
OFF
time (T
OFF(SCP)
= 288 µs typ.) and turns on again for the T
ON
period (T
ON(SCP)
= 130
µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when
no overload is detected (V
FB
> 0.3 V typ.) for the full T
ON
period.
This dynamic operation can greatly reduce the power dissipation in overload conditions,
while still ensuring excellent power-on startup in most conditions.
5.8.5 SCP and OCP operation with high capacitive load
Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from
short circuit and overload.
However, a highly capacitive load on the output may cause difficulties during start-up. This
can be resolved by using the modified application circuit shown in Figure 3, in which a
minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for
C
LOAD
> 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage
divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.
Note that C4 may impact the control loop response and should be added only when a
capacitive load higher than 100 µF is continuously present. If the high capacitive load is
variable or not present at all times, in addition to C4 an increase in the output ceramic
capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also
in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for
C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.