Datasheet

Application information ST1S10
12/29 Doc ID 13844 Rev 5
Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors
usually have very low ESL, making ripple voltages due to the ESL negligible. In order to
reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection
paths should be kept as short as possible.
The ST1S10 has been designed to perform best with ceramic capacitors. Under typical
application conditions a minimum ceramic capacitor value of 22 µF is recommended on the
output, but higher values are suitable considering that the control loop has been designed to
work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF
output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a
47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and
SCP operation Section 5.8.5: SCP and OCP operation with high capacitive load. of this
document.
The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum
output voltage is recommended.
5.4 Output capacitor (0.8 V < V
OUT
< 2.5 V)
For applications with lower output voltage levels (V
out
< 2.5 V) the output capacitance and
inductor values should be selected in a way that improves the DC-DC control loop behavior.
In this output condition two cases must be considered: V
IN
> 8 V and V
IN
< 8 V.
For V
IN
< 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as
shown in Figure 4.
For V
IN
> 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to
the 2 x 22 µF output capacitors as shown in Figure 5.
5.5 Output voltage selection
The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by
connecting a resistor divider (see R1 and R2 in the typical application circuit) between the
output and the V
FB
pin. A resistor divider with R2 in the range of 20 kΩ is a suitable
compromise in terms of current consumption. Once the R2 value is selected, R1 can be
calculated using the following equation:
Equation 6
R1 = R2 x (V
OUT
- V
FB
) / V
FB
where V
FB
= 0.8 V (typ.).
Lower values are suitable as well, but will increase current consumption. Be aware that duty
cycle must be kept below 85% at all application conditions, so that:
Equation 7
D = (V
OUT
+ V
F
) / (V
IN
-V
SW
) < 0.85
where V
F
is the voltage drop across the internal NMOS, and V
SW
represents the voltage
drop across the internal PDMOS.
Note that once the output current is fixed, higher V
OUT
levels increase the power dissipation
of the device leading to an increase in the operating junction temperature. It is