Datasheet

Table Of Contents
ST1S10 Application information
Doc ID 13844 Rev 5 11/29
Equation 2
D = (V
OUT
+ V
F
) / (V
IN
-V
SW
)
where V
F
is the voltage drop across the internal NMOS, and V
SW
represents the voltage
drop across the internal PDMOS. The minimum duty cycle (at V
IN_max
) and the maximum
duty cycle (at V
IN_min
) should be considered in order to determine the max I
RMS
flowing
through the input capacitor.
A minimum value of 4.7 µF for the V
IN_SW
and a 0.1 µF ceramic capacitor for the V
IN_A
are
suitable in most application conditions. A 10 µF or higher ceramic capacitor for the V
IN_SW
and a 1 µF or higher for the V
IN_A
are recommended in cases of higher power supply source
impedance or where long wires are needed between the power supply source and the V
IN
pins. The above higher input capacitor values are also recommended in cases where an
output capacitive load is present (47 µF < C
LOAD
< 100 µF), which could impact the
switching peak current drawn from the input capacitor during the start-up transient.
In cases of very high output capacitive loads (C
LOAD
> 100 µF), all input/output capacitor
values shall be modified as described in the OCP and SCP operation section 5.8.5 of this
document.
The input ceramic capacitors should have a voltage rating in the range of 1.5 times the
maximum input voltage and be located as close as possible to V
IN
pins.
5.3 Output capacitor (V
OUT
> 2.5 V)
The most important parameters for the output capacitor are the capacitance, the ESR and
the voltage rating. The capacitance and the ESR affect the control loop stability, the output
ripple voltage and transient response of the regulator.
The ripple due to the capacitance can be calculated with the following equation:
Equation 3
V
RIPPLE(C)
= (0.125 x I
SW
) / (F
S
x C
OUT
)
where F
S
is the PWM switching frequency and I
SW
is the inductor peak-to-peak switching
current, which can be calculated as:
Equation 4
I
SW
= [(V
IN
- V
OUT
) / (F
S
x L)] x D
where D is the duty cycle.
The ripple due to the ESR is given by:
Equation 5
V
RIPPLE
(ESR) = I
SW
x ESR
The equations above can be used to define the capacitor selection range, but final values
should be verified by testing an evaluation circuit.
Lower ESR ceramic capacitors are usually recommended to reduce the output ripple
voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower
output ripple voltage.