ST1L05 - ST1L05A ST1L05B - ST1L05C - ST1L05D Very low quiescent BiCMOS voltage regulator Features ■ Fixed output voltage: 1.8 V, 2.5 V, 3.3 V and ADJ ■ Output voltage tolerance: ± 2 % at 25 °C ■ Output current capability: 1.3 A ■ Very low quiescent current: max 650 µA Over temperature range ■ Typ. dropout 0.3 V (@ IO =1.
Contents ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Contents 1 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 1 Schematic diagrams Figure 1. Schematic diagram for ST1L05 Schematic diagrams VI VI BandGap reference Current limit OpAmp VO Thermal protection VO_SENSE R1 R2 GND Figure 2.
Schematic diagrams Figure 3. ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Schematic diagram for ST1L05B and ST1L05D VI Power-good signal PG VI BandGap reference Current limit OpAmp VO Thermal protection VI ADJ RP EN Internal enable GND Figure 4.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 2 Pin configuration Figure 5. Pin connections (top through view) ST1L05 Pin configuration ST1L05B ST1L05A ST1L05D ST1L05C Table 2. Pin description Pin n° Symbol Function ST1L05 ST1L05A ST1L05B ST1L05C ST1L05D VI 6 3 6 6 8 Supply voltage input pin. Bypass with a 4.7 µF capacitor to GND VO 4 2 4 4 6 Output voltage pin. Bypass with a 4.
Maximum ratings ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VI DC supply voltage -0.3 to 7 V VO DC output voltage -0.3 to 7 V PG Power Good pin -0.3 to 7 V EN Enable pin -0.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 4 Electrical characteristics Electrical characteristics Refer to the typical application schematic, VI = 3.3 V to 4.5 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at TJ = 25 °C unless otherwise specified. Table 6. Electrical characteristics for the ST1L05PU25 Symbol Parameter Test condition VO Output voltage VI =3.3V to 5.25V, T=25°C VO Output voltage VI = 3.3V to 5.
Electrical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Refer to the typical application schematic, VI = 4.5 V to 5.5 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified). Typical values are intended at TJ = 25 °C unless otherwise specified. Table 7. Electrical characteristics for ST1L05APU33 Symbol Parameter Test condition Min. Typ. Max. Unit VO Output voltage VI = 4.75V to 5.25V, T=25°C 3.234 3.3 3.366 V VO Output voltage VI = 4.75V to 5.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Electrical characteristics Refer to the typical application schematic, VI = 4.5 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at TJ = 25 °C unless otherwise specified. Table 8. Electrical characteristics for the ST1L05CPU33 Symbol Parameter Test condition Min. Typ. Max. Unit VO Output voltage VI = 4.75V to 5.25V, T=25°C 3.234 3.3 3.
Electrical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Refer to the typical application schematic, VI = 3 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A, CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at TJ = 25 °C unless otherwise specified. Table 9. Electrical characteristics for the ST1L05BPU and ST1L05DPU Symbol Parameter Test condition Min. Typ. Max. Unit VO Output voltage VI = 3V to 5.25V, T=25°C 1.195 1.22 1.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Typical characteristics Figure 6. Output voltage vs. temperature 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 Figure 7. VO [V] VO [V] 5 Typical characteristics VEN = VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF -30 -5 20 45 70 95 120 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 145 Output voltage vs. temperature VEN = VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF -30 -5 20 45 T [°C] Figure 8. 2.70 Figure 9. 2.70 2.60 2.60 2.
Typical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Figure 12. Dropout voltage vs. temperature Figure 13. ESR required for stability with ceramic capacitors CI = CO = 4.7 µF, VO @ 3.3 V 0.7 IO = 1 A 0.6 Dropout [V] 0.4 IO = 800 mA ESR @ 100kHz [ohm] 0.8 IO = 1.3 A 0.5 0.4 0.3 0.2 CI = 4.7 µF, VEN = VI = from 3 V to 5.5 V, IO = from 5 mA to 1.3 A 0.35 0.3 0.25 0.2 0.15 0.1 Stable zone 0.05 0.1 0 0 0 -30 -5 20 45 70 95 120 2 4 6 145 T [°C] Figure 14.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Figure 19. Supply voltage rejection vs. frequency 80 80 75 70 70 60 SVR [dB] SVR [dB] Figure 18. Supply voltage rejection vs. temperature Typical characteristics 65 60 VEN = VI = from 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF, F = 120 Hz 55 50 40 30 VEN = VI = 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF 50 20 -30 -5 20 45 70 95 120 145 10 T [°C] 100 1000 10000 100000 1000000 Frequency [Hz] Figure 20.
Application information 6 ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Application information The ST1L05 is a low dropout linear regulator. It provides up to 1.3 A with a low 300 mV dropout. The input voltage range is from 3 V to 5.5 V. The device is available in fixed and adjustable output versions. The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Application information Figure 26. Application schematic for the ST1L05B and ST1L05D VIN PG VIN OFF ON ST1L05B VOUT ST1L05D EN CO ADJ GND CI VOUT R1 R2 GND Figure 27. Application schematic for the ST1L05C VI CI VI OFF ON ST1L05C VO_SENSE EN VO VO GND CO GND For the adjustable version, the output voltage can be adjusted from 1.
Application information 6.1 ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Power dissipation An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 165 °C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the device. It is very important to use a good PC board layout to maximize the power dissipation.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D DFN6D (3x3 mm) mechanical data mm. inch. Dim. Min. A 0.80 A1 0 A3 0.02 Max. Min. 1.00 0.031 0.05 0 0.20 b 0.23 D 2.90 D2 2.23 E 2.90 E2 1.50 e L Typ. 3.00 3.00 0.40 Max. 0.039 0.001 0.002 0.008 0.45 0.009 3.10 0.114 2.50 0.088 3.10 0.114 1.75 0.059 0.95 0.30 Typ. 0.018 0.118 0.122 0.098 0.118 0.122 0.069 0.037 0.50 0.012 0.016 0.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Package mechanical data DFN8 (4x4) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.23 0.30 0.38 0.009 0.012 0.015 D 3.90 4.00 4.10 0.154 0.157 0.161 D2 2.82 3.00 3.23 0.111 0.118 0.127 E 3.90 4.00 4.10 0.154 0.157 0.161 E2 2.05 2.20 2.30 0.081 0.087 0.091 e L 0.80 0.40 0.50 0.031 0.60 0.016 0.020 0.
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Tape & Reel QFNxx/DFNxx (3x3) Mechanical Data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 12.8 D 20.2 0.795 N 60 2.362 0.504 0.519 18.4 0.724 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 14492 Rev 2 Max. 12.992 C T 20/24 Max.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Package mechanical data Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Figure 28. DFN6 (3x3) footprint recommended data Figure 29.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D 8 Revision history Table 10. Document revision history Date Revision 29-Feb-2008 1 First release. 08-Sep-2009 2 Modified Table 1 on page 1.
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.