Datasheet

12 - PARALLEL PORTS ST10F269
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The structure of Port 8 differs in the way the output
latches are connected to the internal bus and to
the pin driver (see Figure 43). Pins P8.7...P8.0
(CC23IO...CC16IO) combine internal bus data
and alternate data output before the port latch
input, as do the Port 2 pins.
Figure 43 : Block Diagram of Port 8 Pins P8.7...P8.0
Open Drain
Latch
Write ODP8.y
Read ODP8.y
Direction
Latch
Write DP8.y
Read DP8.y
Internal Bus
MUX
0
1
Alternate Latch
Data Input
Input
Latch
Clock
P8.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1
Output
Latch
≥ 1
Write Port P8.y
Compare Trigger
Read P8.y
y = (7...0)
z = (16...23)
Alternate Pin
Data Input