Datasheet

12 - PARALLEL PORTS ST10F269
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The structure of Port 7 differs in the way the output
latches are connected to the internal bus and to
the pin driver. Pins P7.3...P7.0 (POUT3...POUT0)
EXOR the alternate data output with the port latch
output, which allows to use the alternate data
directly or inverted at the pin driver.
Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
Internal Bus
MUX
0
1
Input
Latch
Clock
P7.y/POUTy
Output
Buffer
y = 0...3
Port Output
Latch
Read P7.y
Write DP7.y
=1
Port Data
Output
EXOR
Alternate
Data
Output