Datasheet

ST10F269
5/184
TABLE OF CONTENTS PAGE
21.4.7 - Phase Locked Loop .....................................................................................149
21.4.8 - External Clock Drive XTAL1 ........................................................................150
21.4.9 - Memory Cycle Variables .............................................................................151
21.4.10 - Multiplexed Bus ...........................................................................................152
21.4.11 - Demultiplexed Bus ......................................................................................160
21.4.12 - CLKOUT and READY .................................................................................168
21.4.13 - External Bus Arbitration ...............................................................................171
21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ............................174
21.4.14.1Master Mode ................................................................................ 174
21.4.14.2Slave mode .................................................................................. 175
22 - Package Mechanical Data ..................................................................................... 178
23 - Ordering Information ............................................................................................... 180
ERRATA SHEET
1 - DESCRIPTION ....................................................................................................... 181
2 - FUNCTIONAL PROBLEMS .................................................................................... 181
2.1 - PWRDN.1 - EXECUTION OF PWRDN INSTRUCTION .............................................181
2.2 - MAC.9 - COCMP INSTRUCTION INVERTED OPERANDS .......................................182
2.3 - MAC.10 - E FLAG EVALUATION FOR COSHR AND COASHR INSTRUCTIONS WHEN
SATURATION MODE IS ENABLED ...........................................................................182
2.4 - ST_PORT.3 - BAD BEHAVIOR OF HYSTERESIS FUNCTION ON INPUT FALLING
EDGE ..........................................................................................................................183
3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION ............................ 183
4 - ERRATA SHEET VERSION INFORMATION ......................................................... 183