Datasheet

ST10F269 6 - CENTRAL PROCESSING UNIT (CPU)
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6.3 - MAC Coprocessor Specific Instructions
The following table gives an overview of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruction.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction
have been added to the standard instruction set.
Full details are provided in the ‘ST10 Family Pro-
gramming Manual’. Double indirect addressing
requires two pointers. Any GPR can be used for
one pointer, the other pointer is provided by one of
two specific SFRs IDX0 and IDX1. Two pairs of
offset registers QR0/QR1 and QX0/QX1 are asso-
ciated with each pointer (GPR or IDX
i
).
The GPR pointer allows access to the entire
memory space, but IDX
i
are limited to the internal
Dual-Port RAM, except for the CoMOV instruction.
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update register with word
operand
4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack
2
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI
-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Table 4 : Instruction Set Summary
Mnemonic Description Bytes