Datasheet
ST10F269 5 - INTERNAL FLASH MEMORY
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Table 3 : Instructions
Notes 1. Address bit A14, A15 and above are don’t care for coded address inputs.
2. X = Don’t Care.
3. WA = Write Address: address of memory location to be programmed.
4. WD = Write Data: 16-bit data to be programmed
5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, time-out status can be
verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
6. Read Data Polling or Toggle bit until Erase completes.
7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR must be
‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0’).
Instruction Mne Cycle
1
st
Cycle
2
nd
Cycle
3
rd
Cycle 4
th
Cycle
5
th
Cycle
6
th
Cycle
7
th
Cycle
Read/Reset RD 1+
Addr.
1
X
2
Read Memory Array until a new write cycle is initiated
Data xxF0h
Read/Reset RD 3+
Addr.
1
x1554h x2AA8h xxxxxh
Read Memory Array until a new write
cycle is initiated
Data xxA8h xx54h xxF0h
Program Word PW 4
Addr.
1
x1554h x2AA8h x1554h
WA
3
Read Data Polling or Tog-
gle bit until Program com-
pletes.
Data xxA8h xx54h xxA0h
WD
4
Block Erase BE 6
Addr.
1
x1554h x2AA8h x1554h x1554h x2AA8h BA
BA’
5
Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h
Chip Erase CE 6
Addr.
1
x1554h x2AA8h x1554h x1554h x2AA8h x1554h
Note
6
Data xxA8h xx54h xx80h xxA8h xx54h xx10h
Erase Suspend ES 1
Addr.
1
X
2
Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Data xxB0h
Erase Resume ER 1
Addr.
1
X
2
Read Data Polling or Toggle bit until Erase completes or Erase is
suspended another time.
Data xx30h
Set Block/Code
Protection
SP 4
Addr.
1
x2A54h x15A8h x2A54h Any odd
word
address
9
Data xxA8h xx54h xxC0h
WPR
7
Read
Protection
Status
RP 4
Addr.
1
x2A54h x15A8h x2A54h Any odd
word
address
9
Read Protection Register
until a new write cycle is
initiated.
Data xxA8h xx54h xx90h Read PR
Block
Temporary
Unprotection
BTU 4
Addr.
1
x2A54h x15A8h x2A54h
X
2
Data xxA8h xx54h xxC1h xxF0h
Code
Temporary
Unprotection
CTU 1
Addr.
1
MEM
8
Write cycles must be executed from Flash.
Data FFFFh
Code
Temporary
Protection
CTP 1
Addr.
1
MEM
8
Write cycles must be executed from Flash.
Data FFFBh