Datasheet

ST10F269
177/184
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge
(drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO =
0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Figure 83 : SSC Slave Timing
t
313
t
314
t
315
t
315
t
315
t
316
1st Out Bit Last Out Bit2nd Out Bit
t
310
t
312
t
311
1)
2)
t
317
2nd.In Bit1st.In Bit
t
318
t
317
Last.In Bit
t
318
SCLK
MRST
MTSR