Datasheet

ST10F269
176/184
The formula for SSC Clock Cycle time is: t
310
= 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
V
CC
= 5V ±10%, V
SS
= 0V, CPU clock = 32MHz, T
A
= -40 to +125°C, C
L
= 50pF (TQFP144 devices)
The formula for SSC Clock Cycle time is: t
310
= 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer
t
317
SR Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
6–6–ns
t
318
SR Read data hold time after latch edge,
phase error detection off
(SSCPEN = 0)
31 – 2TCL + 6 – ns
Symbol Parameter
Maximum Baud rate=10MBd
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Unit
Minimum Maximum Minimum Maximum
Symbol Parameter
Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Unit
Minimum Maximum Minimum Maximum
t
310
SR SSC clock cycle time 125 – 8 TCL 262144 TCL ns
t
311
SR SSC clock high time 52.5 –
t
310
/2 - 10
–ns
t
312
SR SSC clock low time 52.5 –
t
310
/2 - 10
–ns
t
313
SR SSC clock rise time – 10 – 10 ns
t
314
SR SSC clock fall time – 10 – 10 ns
t
315
CC Write data valid after shift edge – 45.25 – 2 TCL + 14 ns
t
316
CC Write data hold after shift edge 0 – 0 – ns
t
317p
SR Read data setup time before latch edge,
phase error detection on (SSCPEN = 1)
78.125 – 4TCL +
15.625
–ns
t
318p
1
SR Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
109.375 – 6TCL +
15.625
–ns
t
317
SR Read data setup time before latch edge,
phase error detection off (SSCPEN = 0)
6–6–ns
t
318
SR Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
41.25 – 2TCL + 10 – ns