Datasheet

ST10F269
175/184
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is : t
300
= 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge
(drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO =
0b).
2. The bit timing is repeated for all bits to be transmitted or received.
21.4.14.2 Slave mode
V
CC
= 5V ±10%, V
SS
= 0V, CPU clock = 40MHz, T
A
= -40 to +125°C, C
L
= 50pF (PQFP144 devices)
t
318
SR Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
41.25 – 2TCL + 10 –
t
318
Symbol Parameter
Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Symb
ol
Minimum Maximum Minimum Maximum
Figure 82 : SSC Master Timing
t
303
t
304
t
305
t
305
t
305
t
306
1st Out Bit Last Out Bit2nd Out Bit
t
300
t
302
t
301
1)
2)
t
307
2nd.In Bit
1st.In Bit
t
308
t
307
Last.In Bit
t
308
SCLK
MTSR
MRST
Symbol Parameter
Maximum Baud rate=10MBd
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Unit
Minimum Maximum Minimum Maximum
t
310
SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t
311
SR SSC clock high time 40 –
t
310
/2 - 10
–ns
t
312
SR SSC clock low time 40 –
t
310
/2 - 10
–ns
t
313
SR SSC clock rise time – 10 – 10 ns
t
314
SR SSC clock fall time – 10 – 10 ns
t
315
CC Write data valid after shift edge – 39 – 2 TCL + 14 ns
t
316
CC Write data hold after shift edge 0 – 0 – ns
t
317p
SR Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
62 – 4TCL + 12 – ns
t
318p
1
SR Read data hold time after latch edge,
phase error detection on
(SSCPEN = 1)
87 – 6TCL + 12 – ns