Datasheet

ST10F269
174/184
21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing
21.4.14.1 Master Mode
V
CC
= 5V ±10%, V
SS
= 0V, CPU clock = 40MHz, T
A
= -40 to +125°C, C
L
= 50pF (PQFP144 devices)
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is: t
300
= 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
V
CC
= 5V ±10%, V
SS
= 0V, CPU clock = 32MHz, T
A
= -40 to +125°C, C
L
= 50pF (TQFP144 devices)
Symbol Parameter
Maximum Baud rate = 10M Baud
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Unit
Minimum Maximum Minimum Maximum
t
300
CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t
301
CC SSC clock high time 40 –
t
300
/2 - 10
–ns
t
302
CC SSC clock low time 40 –
t
300
/2 - 10
–ns
t
303
CC SSC clock rise time – 10 – 10 ns
t
304
CC SSC clock fall time – 10 – 10 ns
t
305
CC Write data valid after shift edge – 15 – 15 ns
t
306
CC
Write data hold after shift edge
1
-2 – -2 – ns
t
307p
SR Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
37.5 – 2TCL+12.5 – ns
t
308p
SR Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
50 – 4TCL – ns
t
307
SR Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
25 – 2TCL – ns
t
308
SR Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
0–0–ns
Symbol Parameter
Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h)
Variable Baud rate
(<SSCBR>=0001h-FFFFh)
Symb
ol
Minimum Maximum Minimum Maximum
t
310
SR SSC clock cycle time 125 – 8 TCL 262144 TCL
t
310
t
311
SR SSC clock high time 52.5 –
t
310
/2 - 10
–
t
311
t
312
SR SSC clock low time 52.5 –
t
310
/2 - 10
–
t
312
t
313
SR SSC clock rise time – 10 – 10
t
313
t
314
SR SSC clock fall time – 10 – 10
t
314
t
315
CC Write data valid after shift edge – 45.25 – 2 TCL + 14
t
315
t
316
CC Write data hold after shift edge 0 – 0 –
t
316
t
317p
SR Read data setup time before latch edge,
phase error detection on (SSCPEN = 1)
78.125 – 4TCL +
15.625
–
t
317p
t
318p
1
SR Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
109.375 – 6TCL +
15.625
–
t
318p
1
t
317
SR Read data setup time before latch edge,
phase error detection off (SSCPEN = 0)
6–6–
t
317