Datasheet

ST10F269
171/184
21.4.13 - External Bus Arbitration
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF (PQFP144 devices)
Note: 1. Partially tested, guaranteed by design characterization
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF (TQFP144 devices)
Note: 1. Partially tested, guaranteed by design characterization
Symbol Parameter
Maximum CPU Clock
= 40 MHz
Variable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Minimum Maximum Minimum Maximum
t
61 SR
HOLD input setup time
to CLKOUT
15 – 15 – ns
t
62 CC
CLKOUT to HLDA high
or BREQ
low delay
– 12.5 – 12.5 ns
t
63 CC
CLKOUT to HLDA low
or BREQ
high delay
– 12.5 – 12.5 ns
t
64 CC CSx release
1
– 15 – 15 ns
t
65 CC
CSx drive -4 15 -4 15 ns
t
66 CC Other signals release
1
– 15 – 15 ns
t
67 CC
Other signals drive -4 15 -4 15 ns
Symbol Parameter
Maximum CPU Clock
= 32MHz
Variable CPU Clock
1/2TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t
61 SR
HOLD input setup time
to CLKOUT
20 – 20 – ns
t
62 CC
CLKOUT to HLDA high
or BREQ
low delay
– 15.625 – 15.625 ns
t
63 CC
CLKOUT to HLDA low
or BREQ
high delay
– 15.625 – 15.625 ns
t
64 CC
CSx release
1
–15 – 15ns
t
65 CC
CSx drive -4 15 -4 15 ns
t
66 CC
Other signals release
1
–15 – 15ns
t
67 CC
Other signals drive -4 15 -4 15 ns