Datasheet

ST10F269
169/184
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to + 125°C, C
L
= 50pF, TQFP144 devices
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
Note 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2t
A
and t
C
refer to the next following bus cycle, t
F
refers to the current bus cycle.
Table 51 : CLKOUT and READY Characteristics (TQFP144 devices)
Symbol Parameter
Maximum CPU Clock
= 32MHz
Variable CPU Clock
1/2TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t
29
CC CLKOUT cycle time 31.25 31.25 2TCL 2TCL ns
t
30
CC CLKOUT high time 9.625 – TCL – 6 – ns
t
31
CC CLKOUT low time 5.625 – TCL – 10 – ns
t
32
CC CLKOUT rise time – 4 – 4 ns
t
33
CC CLKOUT fall time – 4 – 4 ns
t
34
CC CLKOUT rising edge to
ALE falling edge
-3 + t
A
+7 + t
A
-3 + t
A
+7 + t
A
ns
t
35
SR Synchronous READY
setup time to CLKOUT
14 – 14 – ns
t
36
SR Synchronous READY
hold time after CLKOUT
4– 4 –ns
t
37
SR Asynchronous READY
low time
45.25 – 2TCL + 14 – ns
t
58
SR Asynchronous READY
setup time
1)
14 – 14 – ns
t
59
SR Asynchronous READY
hold time
1)
4– 4 –ns
t
60
SR Async. READY hold time after
RD
, WR high (Demultiplexed
Bus)
2)
00 + 2t
A
+ t
C
+ t
F
2
0 TCL - 15.625 +
2t
A
+ t
C
+ t
F
2
ns