Datasheet
ST10F269
166/184
Figure 77 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
Data In
Data Out
t
5 t
16
t
51
t
46
t
50
t
48
Address
t
17
t
49
t
47
t
48
t
49
t
68
t
53
t
83
t
82
t
26
t
57
t
55
t
6
t
82
t
83
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE