Datasheet

ST10F269
165/184
Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended
ALE
Address
t
5
t
16
t
39
t
41
t
14
t
24
t
6
t
38
t
20
t
26
t
17
t
15
t
12
t
13
t
12
t
13
t
22
Data In
t
18
t
21
t
6
t
17
t
28
t
28
Data Out
t
80
t
81
t
80
t
81
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
RD
WR
WRL
WRH
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE