Datasheet

ST10F269
164/184
Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE
Note: 1. Un-latched CSx = t
41u
= t
41
TCL =10.5 + t
F
.
Write Cycle
CLKOUT
ALE
A23-A16
A15-A0 (P1)
BHE
WR
WRL
WRH
Data In
Data Out
t
38
t
5 t
16
t
39
t
41
t
18
t
14
t
22
t
12
Address
t
17
t
13
t
15
t
12
t
13
t
21
t
20
t
81
t
80
t
26
t
24
t
17
t
6
t
41u
t
6
t
80
t
81
t
28
(or t
28h
)
CSx
Read Cycle
Data Bus (P0)
RD
1)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0