Datasheet
ST10F269
163/184
Notes: 1. RW-delay and t
A
refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD
edge. Therefore address
changes before the end of RD
have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
t
48
CC RdCS, WrCS Low Time
(with RW-delay)
21.25 + t
C
– 2TCL - 10 + t
C
–ns
t
49
CC RdCS, WrCS Low Time
(no RW-delay)
36.875 + t
C
– 3TCL - 10 + t
C
–ns
t
50
CC Data valid to WrCS 17.25 + t
C
– 2TCL - 14 + t
C
–ns
t
51
SR Data hold after RdCS 0– 0 –ns
t
53
SR Data float after RdCS
(with RW-delay)
3
– 21.25 + t
F
– 2TCL - 10 + t
F
ns
t
68
SR Data float after RdCS
(no RW-delay)
3
–0 + t
F
–TCL - 10 + t
F
ns
t
55
CC Address hold after
RdCS
, WrCS
-10 + t
F
– -10 + t
F
–ns
t
57
CC Data hold after WrCS 1.625 + t
F
–TCL - 14 + t
F
–ns
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum