Datasheet

ST10F269
162/184
t
81
CC Address/Unlatched CS setup
to RD
, WR
(no RW-delay)
5.625 + 2t
A
–TCL -10 + 2t
A
–ns
t
12
CC RD, WR low time
(with RW-delay)
21.25 + t
C
– 2TCL - 10 + t
C
–ns
t
13
CC RD, WR low time
(no RW-delay)
36.875 + t
C
– 3TCL - 10 + t
C
–ns
t
14
SR RD to valid data in
(with RW-delay)
– 11.25 + t
C
– 2TCL - 20 + t
C
ns
t
15
SR RD to valid data in
(no RW-delay)
– 26.875 + t
C
– 3TCL - 20 + t
C
ns
t
16
SR ALE low to valid data in – 26.875 + t
A
+
t
C
–3TCL - 20
+ t
A
+ t
C
ns
t
17
SR Address/Unlatched CS to
valid data in
– 32.5 + 2t
A
+
t
C
– 4TCL - 30
+ 2t
A
+ t
C
ns
t
18
SR Data hold after RD
rising edge
0– 0 –ns
t
20
SR Data float after RD rising
edge (with RW-delay)
1 - 3
– 26 + t
F
– 2TCL - 14
+ t
F
+ 2t
A
1
ns
t
21
SR Data float after RD rising
edge (no RW-delay)
1 - 3
– 5.625 + t
F
–TCL - 10
+ t
F
+ 2t
A
1
ns
t
22
CC Data valid to WR 11.25 + t
C
– 2TCL- 20 + t
C
–ns
t
24
CC Data hold after WR 5.625 + t
F
–TCL - 10+ t
F
–ns
t
26
CC ALE rising edge after RD, WR -10 + t
F
– -10 + t
F
–ns
t
28
CC Address/Unlatched CS hold
after RD
, WR
2
0 (no t
F
)
-5 + t
F
(t
F
> 0)
– 0 (no t
F
)
-5 + t
F
(t
F
> 0)
–ns
t
28h
CC Address/Unlatched CS hold
after WRH
-5 + t
F
–-5 + t
F
–ns
t
38
CC ALE falling edge to Latched
CS
-4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
t
39
SR Latched CS low to Valid Data
In
– 26.875 + t
C
+
2t
A
– 3TCL - 20
+ t
C
+ 2t
A
ns
t
41
CC Latched CS hold after RD,
WR
1.625 + t
F
–TCL - 14 + t
F
–ns
t
82
CC Address setup to RdCS,
WrCS
(with RW-delay)
17.25 + 2t
A
– 2TCL - 14 + 2t
A
–ns
t
83
CC Address setup to RdCS,
WrCS
(no RW-delay)
1.625 + 2t
A
–TCL -14 + 2t
A
–ns
t
46
SR RdCS to Valid Data In
(with RW-delay)
– 7.25 + t
C
– 2TCL - 24 + t
C
ns
t
47
SR RdCS to Valid Data In
(no RW-delay)
– 22.875 + t
C
– 3TCL - 24 + t
C
ns
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum