Datasheet

ST10F269
161/184
Notes: 1. RW-delay and t
A
refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD
edge. Therefore address
changes before the end of RD
have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +85°C, C
L
= 50pF,
ALE cycle time = 4 TCL + 2t
A
+ t
C
+ t
F
(125ns at 32MHz CPU clock without wait states) RW-delay and t
A
refer to the next following bus cycle.
Table 49 : Demultiplexed Bus Characteristics (TQFP144 devices)
t
41
CC Latched CS hold after RD, WR 2 + t
F
TCL - 10.5 + t
F
–ns
t
82
CC Address setup to RdCS, WrCS
(with RW-delay)
14.5 + 2t
A
2 TCL - 10.5 +
2t
A
–ns
t
83
CC Address setup to RdCS, WrCS
(no RW-delay)
2 + 2t
A
TCL - 10.5 + 2t
A
–ns
t
46
SR RdCS to Valid Data In
(with RW-delay)
–4 + t
C
2 TCL - 21 + t
C
ns
t
47
SR RdCS to Valid Data In
(no RW-delay)
16.5 + t
C
3 TCL - 21 + t
C
ns
t
48
CC RdCS, WrCS Low Time
(with RW-delay)
15.5 + t
C
–2 TCL - 9.5
+ t
C
–ns
t
49
CC RdCS, WrCS Low Time
(no RW-delay)
28 + t
C
3 TCL - 9.5 + t
C
–ns
t
50
CC Data valid to WrCS 10 + t
C
2 TCL - 15 + t
C
–ns
t
51
SR Data hold after RdCS 0– 0 ns
t
53
SR Data float after RdCS
(with RW-delay)
3
16.5 + t
F
2 TCL - 8.5 + t
F
ns
t
68
SR Data float after RdCS
(no RW-delay)
3
–4 + t
F
TCL - 8.5 + t
F
ns
t
55
CC Address hold after
RdCS
, WrCS
-8.5 + t
F
-8.5 + t
F
–ns
t
57
CC Data hold after WrCS 2 + t
F
TCL - 10.5 + t
F
–ns
Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Maximum CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t
5
CC ALE high time 5.625 + t
A
–TCL - 10+ t
A
–ns
t
6
CC Address setup to ALE 0.625 + t
A
–TCL - 15+ t
A
–ns
t
80
CC Address/Unlatched CS setup
to RD
, WR
(with RW-delay)
21.25 + 2t
A
2TCL - 10 + 2t
A
–ns