Datasheet

ST10F269
160/184
21.4.11 - Demultiplexed Bus
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF,
ALE cycle time = 4 TCL + 2t
A
+ t
C
+ t
F
(50ns at
40MHz CPU clock without wait states), PQFP144
devices.
Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Maximum CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t
5
CC ALE high time 4 + t
A
–TCL - 8.5 + t
A
–ns
t
6
CC Address setup to ALE 2 + t
A
– TCL - 10.5 + t
A
–ns
t
80
CC Address/Unlatched CS setup to
RD
, WR
(with RW-delay)
16.5 + 2t
A
– 2 TCL - 8.5 + 2t
A
–ns
t
81
CC Address/Unlatched CS setup to
RD
, WR
(no RW-delay)
4 + 2t
A
– TCL - 8.5 + 2t
A
–ns
t
12
CC RD, WR low time
(with RW-delay)
15.5 + t
C
– 2 TCL - 9.5 + t
C
–ns
t
13
CC RD, WR low time
(no RW-delay)
28 + t
C
– 3 TCL - 9.5 + t
C
–ns
t
14
SR RD to valid data in
(with RW-delay)
–6 + t
C
– 2 TCL - 19 + t
C
ns
t
15
SR RD to valid data in
(no RW-delay)
– 18.5 + t
C
– 3 TCL - 19 + t
C
ns
t
16
SR ALE low to valid data in – 18.5 + t
A
+
t
C
–3 TCL - 19
+ t
A
+ t
C
ns
t
17
SR Address/Unlatched CS to valid
data in
–22 + 2t
A
+
t
C
–4 TCL - 28
+ 2t
A
+ t
C
ns
t
18
SR Data hold after RD
rising edge
0– 0 –ns
t
20
SR Data float after RD rising edge
(with RW-delay)
1 3
– 16.5 + t
F
–2 TCL - 8.5
+ t
F
+ 2t
A
1
ns
t
21
SR Data float after RD rising edge
(no RW-delay)
1 3
–4 + t
F
–TCL - 8.5
+ t
F
+ 2t
A
1
ns
t
22
CC Data valid to WR 10 + t
C
– 2 TCL - 15 + t
C
–ns
t
24
CC Data hold after WR 4 + t
F
– TCL - 8.5 + t
F
–ns
t
26
CC ALE rising edge after RD, WR -10 + t
F
– -10 + t
F
–ns
t
28
CC Address/Unlatched CS hold
after RD
, WR
2
0 (no t
F
)
-5 + t
F
(t
F
> 0)
– 0 (no t
F
)
-5 + t
F
(t
F
> 0)
–ns
t
28h
CC Address/Unlatched CS hold
after WRH
-5 + t
F
–-5 + t
F
–ns
t
38
CC ALE falling edge to Latched CS -4 - t
A
6 - t
A
-4 - t
A
6 - t
A
ns
t
39
SR Latched CS low to Valid Data In – 18.5
+ t
C
+ 2t
A
–3 TCL - 19
+ t
C
+ 2t
A
ns