Datasheet

ST10F269
157/184
Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE
Data Out
Address
Data In
Address
Address
t
5
t
16
t
6
t
7
t
39
t
40
t
14
t
8
t
18
t
23
t
6
t
27
t
38
t
10
t
19
t
25
t
17
t
9
t
11
t
15
t
12
t
13
t
8
t
10
t
9
t
11
t
12
t
13
t
22
t
27
t
17
t
6
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
RD
WR
WRL
BHE
WRH
Address/Data
Bus (P0)
Address/Data
Bus (P0)