Datasheet

ST10F269
156/184
Figure 71 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE
Data In
Data Out
Address
Address
t
38
t
10
Read Cycle
Write Cycle
t
5
t
16
t
39
t
40
t
25
t
27
t
18
t
14
t
22
t
23
t
12
t
8
t
8
t
6m
t
19
Address
t
17
t
6
t
7
t
9
t
11
t
13
t
15
t
16
t
12
t
13
Address
t
9
t
17
t
6
t
27
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
Address/Data
RD
WR
WRL
BHE
WRH
Bus (P0)
Address/Data
Bus (P0)