Datasheet

ST10F269
155/184
1. Partially tested, guaranted by design characterization.
t
44
CC
Address float after RdCS
,
WrCS (with RW delay) 1
–0 – 0ns
t
45
CC
Address float after RdCS
,
WrCS (no RW delay) 1
– 15.625 – TCL ns
t
46
SR
RdCS
to Valid Data In
(with RW delay)
– 7.25 + t
C
– 2TCL - 24 + t
C
ns
t
47
SR
RdCS
to Valid Data In
(no RW delay)
– 22.875 + t
C
– 3TCL - 24 + t
C
ns
t
48
CC
RdCS
, WrCS Low Time
(with RW delay)
21.25 + t
C
– 2TCL - 10 + t
C
–ns
t
49
CC
RdCS
, WrCS Low Time
(no RW delay)
36.875 + t
C
– 3TCL - 10 + t
C
–ns
t
50
CC
Data valid to WrCS
17.25 + t
C
–2TCL - 14+ t
C
–ns
t
51
SR
Data hold after RdCS
0– 0 –ns
t
52
SR
Data float after RdCS
1
– 11.25 + t
F
– 2TCL - 20 + t
F
ns
t
54
CC
Address hold after
RdCS, WrCS
11.25 + t
F
– 2TCL - 20 + t
F
–ns
t
56
CC
Data hold after WrCS
11.25 + t
F
– 2TCL - 20 + t
F
–ns
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum