Datasheet

ST10F269
154/184
t
9
CC
ALE falling edge to RD
, WR (no
RW-delay)
-10 + t
A
–-10 + t
A
–ns
t
10
CC
Address float after RD
, WR
(with RW-delay) 1
–6 – 6ns
t
11
CC
Address float after RD
, WR
(no RW-delay) 1
– 21.625 – TCL + 6 ns
t
12
CC
RD
, WR low time
(with RW-delay)
21.25 + t
C
– 2TCL - 10 + t
C
–ns
t
13
CC
RD
, WR low time
(no RW-delay)
36.875 + t
C
– 3TCL - 10 + t
C
–ns
t
14
SR
RD
to valid data in
(with RW-delay)
– 11.25 + t
C
– 2TCL - 20+ t
C
ns
t
15
SR
RD
to valid data in
(no RW-delay)
– 26.875 + t
C
– 3TCL - 20+ t
C
ns
t
16
SR
ALE low to valid data in – 26.875 + t
A
+ t
C
– 3TCL - 20
+ t
A
+ t
C
ns
t
17
SR
Address/Unlatched CS
to valid
data in
– 32.5 + 2t
A
+ t
C
– 4TCL - 30
+ 2t
A
+ t
C
ns
t
18
SR
Data hold after RD
rising edge
0– 0 –ns
t
19
SR
Data float after RD
1
– 17.25 + t
F
– 2TCL - 14 + t
F
ns
t
22
CC
Data valid to WR
11.25 + t
C
– 2TCL - 20 + t
C
–ns
t
23
CC
Data hold after WR
17.25 + t
F
– 2TCL - 14 + t
F
–ns
t
25
CC
ALE rising edge after RD
, WR 17.25 + t
F
– 2TCL - 14 + t
F
–ns
t
27
CC
Address/Unlatched CS
hold
after RD
, WR
17.25 + t
F
– 2TCL - 14 + t
F
–ns
t
38
CC
ALE falling edge to Latched CS
-4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
t
39
SR
Latched CS
low to Valid Data In – 26.875 + t
C
+ 2t
A
– 3TCL - 20
+ t
C
+ 2t
A
ns
t
40
CC
Latched CS
hold after RD, WR 32.875 + t
F
– 3TCL - 14 + t
F
–ns
t
42
CC
ALE fall. edge to RdCS
, WrCS
(with RW delay)
11.625 + t
A
–TCL - 4 + t
A
–ns
t
43
CC
ALE fall. edge to RdCS
, WrCS
(no RW delay)
-4 + t
A
–-4 + t
A
–ns
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum